Dynamic Random Access Memory For Communications Systems

ABSTRACT

An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, and DRAM cells. A first portion of the DRAM cells may be refreshed by the memory refresh circuit. The DRAM cells store data received via a communication link and a rate at which the first portion of the DRAM cells is refreshed may be adjusted based on a symbol rate at which the data is received via the communication link. The DRAM cells may include one-transistor (“1T”) cells. The adjustment of the rate at which the first portion of the DRAM cells is refreshed may include an enabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a first time interval and a disabling of refresh of the first portion of the DRAM cells by the memory refresh circuit during a second time interval.

CLAIM OF PRIORITY

This patent application is a continuation of U.S. patent applicationSer. No. 14/874,992 filed on Oct. 5, 2015, which is a continuation ofU.S. patent application Ser. No. 14/156,792 filed on Jan. 16, 2014, nowU.S. Pat. No. 9,153,310, which in turn, claims priority to U.S.Provisional Patent Application No. 61/753,237, which was filed on Jan.16, 2013. Each of the above reference documents is hereby incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

Conventional systems and methods for communications can be overly powerhungry, slow, expensive, and inflexible. Further limitations anddisadvantages of conventional and traditional approaches will becomeapparent to one of skill in the art, through comparison of such systemswith some aspects of the present invention as set forth in the remainderof the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

Systems and methods for communications, substantially as shown in and/ordescribed in connection with at least one of the figures, as set forthmore completely in the claims.

Advantages, aspects and novel features of the present disclosure, aswell as details of various implementations thereof, will be more fullyunderstood from the following description and drawings.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 depicts an example communication system comprising memory cellsoptimized for use in an error-tolerant system.

FIG. 2 is a block diagram illustrating a system comprising“non-refreshed” dynamic random access memory (NDRAM) and “refreshed”dynamic random access memory (RDRAM).

FIG. 3 is an example receiver system in which RDRAM is used for storingbits that are replaced/overwritten slowly/infrequently, whereas NDRAM isused for storing bits that are replaced/overwritten quickly/frequently.

FIG. 4 depicts an example system which is configurable such that in afirst mode an array of DRAM cells is used as RDRAM and in a second modethe array is used as NDRAM.

FIG. 5A depicts an example one-transistor (“1T”) DRAM cell.

FIG. 5B depicts an example six-transistor (“6T”) SRAM cell.

FIGS. 6A-6C illustrate aspects of sizing RDRAM and NDRAM cells.

FIGS. 7A-7C depict memory arrays where different types of memory cellsare used based on the significance/sensitivity of the bit being stored.

DETAILED DESCRIPTION OF THE INVENTION

As utilized herein the terms “circuits” and “circuitry” refer tophysical electronic components (i.e. hardware) and any software and/orfirmware (“code”) which may configure the hardware, be executed by thehardware, and or otherwise be associated with the hardware. As usedherein, for example, a particular processor and memory may comprise afirst “circuit” when executing a first one or more lines of code and maycomprise a second “circuit” when executing a second one or more lines ofcode. As utilized herein, “and/or” means any one or more of the items inthe list joined by “and/or”. As an example, “x and/or y” means anyelement of the three-element set {(x), (y), (x, y)}. As another example,“x, y, and/or z” means any element of the seven-element set {(x), (y),(z), (x, y), (x, z), (y, z), (x, y, z)}. As utilized herein, the term“exemplary” means serving as a non-limiting example, instance, orillustration. As utilized herein, the terms “e.g.,” and “for example”set off lists of one or more non-limiting examples, instances, orillustrations. As utilized herein, circuitry is “operable” to perform afunction whenever the circuitry comprises the necessary hardware andcode (if any is necessary) to perform the function, regardless ofwhether performance of the function is disabled, or not enabled, by someuser-configurable setting.

FIG. 1 depicts an example communication system comprising memory cellsoptimized for use in an error-tolerant system. In an exampleimplementation depicted, the communication system comprises a system onchip (SoC) 102. For example, the SoC 102 may be integrated on a singlesilicon die. The SoC 102 comprises an RF/Analog front-end circuit 104,digital signal processing (DSP) circuit 106, one or more arrays ofdynamic random access memory (DRAM) 108, one or more arrays of staticrandom access memory (SRAM), and a processor 112.

The front-end circuit 104 is operable to interface the SoC 102 to acommunication medium (e.g., wired bus or cable, optical fiber, orwireless channel). In instances that the front-end 104 is configured forreception, it may comprise, for example, a low noise amplifier, a mixer,a filter, and an analog to digital converter. In instances that thefront-end 104 is configured for transmission, it may comprise, forexample, a digital to analog converter, a filter, a mixer, and a poweramplifier.

The processor 112 is operable to execute instructions (e.g., stored inthe DRAM 108 and/or the SRAM 110) to control operations of the SoC 102.This may comprise, for example, configuring the front-end 104,configuring the DSP 106, and controlling reads and writes to/from theDRAM 108 and the SRAM 110.

The DSP 106 is operable to process digital signals. In this regard, theDSP 106 may comprise, for example, an equalizer, a detector, ade-mapper, a decoder, and/or the like.

The SRAM 110 comprises one or more arrays of SRAM memory cells. Thearrays may range in size from a single-bit to multiple megabits, ormore. For example, each array of one or more SRAM cells may comprise oneor more pages/rows distributed across one or more banks, with eachpage/row consisting of one or more columns, each column corresponding toparticular address, and each column consisting of one or more cells. Forexample, array 110 ₁ may be a relatively large number of SRAM cellswhereas each of arrays 110 ₂ and 110 ₃ may comprise a relatively smallnumber of SRAM cells. In an example implementation, each SRAM cell maybe a six-transistor (“6T”) cell, such as is shown in FIG. 5B. Thetransistors, M₁ through M₆, of each SRAM cell on the SoC 102 may berealized using the same fabrication process and same process designrules as the transistors of the SoC 102 that realize the digital logic.

Referring back to FIG. 1, the DRAM 108 comprises one or more arrays ofDRAM memory cells. The arrays may range in size from a single-bit tomultiple megabits, or more. For example, each array of one or more DRAMcells may comprise one or more pages/rows distributed across one or morebanks, with each page/row consisting of one or more columns/addresses,and each column/address consisting of one or more cells. For example,array 108 ₁ may be a relatively large number of DRAM cells whereas eachof arrays 108 ₂ and 108 ₃ may comprise a relatively small number of DRAMcells. In an example implementation, each DRAM cell may be aone-transistor (“1T”) cell, such as is shown in FIG. 5A. The transistor,M, of each DRAM cell on the SoC 102 may be realized using the samefabrication process and same process design rules as the transistors ofthe SoC 102 that realize, for example, digital logic and M₁ through M₆of the SRAM cells. This is in contrast to dedicated DRAM chips whichoften use semiconductor processes specialized for fabricating DRAMcells.

Referring now to FIG. 2, there is again shown the SoC 102. In FIG. 2,components of SoC 102 other than DRAM arrays 204 and 206, and memoryrefresh circuit 202, are omitted for clarity of illustration.

A DRAM cell stores a bit as the presence or absence of an electriccharge on a capacitor. Because this charge inevitably leaks away due tonon-idealities, eventually (after some time duration D) enough chargewill leak away that the value of the bit is no longer sufficientlyreliable (e.g., probability of error is greater than some thresholdT_(ERR)). To prevent this loss of stored information, DRAM cells areconventionally refreshed at intervals of duration less than D. Ineffect, a refresh of a DRAM cell comprises reading the cell andimmediately writing the read value back to the cell (restoring theamount of charge on the capacitor).

Each of the DRAM arrays 204 and 206 may correspond to a respective oneof the arrays of DRAM 108 of FIG. 1. The DRAM array 204 is coupled tomemory refresh circuit 202, and the memory refresh circuit 202 may bededicated circuitry for performing refreshes of the array 204. The array204 is accordingly referred to herein as “refreshed DRAM (RDRAM)”.

There is no refresh circuitry coupled to the array 206. The array 206 isaccordingly referred to herein as “non-refreshed DRAM (NDRAM)”.Consequently, if a value sits in array 206 for longer than D theprobability of reading an incorrect value from the array is greater thansome determined threshold T_(ERR). If, however, new values are writtento array 206 at intervals that are shorter in duration than D, thensignificant time, power, and/or area overhead may be saved by notrefreshing array 206 and/or not having refresh circuitry for array 206at all.

In an example implementation, the SoC may not comprise any RDRAM cellsand may, therefore, not comprise any DRAM refresh circuit.

FIG. 3 is an example receiver system in which RDRAM is used for storingbits that are replaced/overwritten slowly/infrequently, whereas NDRAM isused for storing bits that are replaced/overwritten quickly/frequently.Shown in FG. 3, is an equalizer 320, a demapper 322, a deinterleaver324, and a decoder 326. The components of FIG. 3 may, for example,reside in an example implementation of DSP circuit 106. Although theDRAM in FIG. 3 is depicted as eight arrays 304 ₁-304 ₄ and 306 ₁-306 ₄,physically the arrays may be grouped into any number of one or moregrids.

For purposes of FIG. 3, it is assumed that all DRAM cells of arrays 304₁-304 ₄ and 306 ₁-306 ₄ have substantially the same layout (e.g., sametransistor size, capacitor size, arrangement/orientation, and/or thelike). Consequently, it is assumed that each of the DRAM cells of arrays304 ₁-304 ₄ and 306 ₁-306 ₄ is characterized by the same value of D. Inother implementations, cells of the various arrays 304 and 306 may bedifferently sized based on various factors such as, for example: therate of change/replacement of information that the cell is to store, theerror tolerance of the information that the cell is to store, whether itis to operate as an RDRAM cell or an NDRAM cell. Additional details ofsizing RDRAM and NDRAM cells are described below with reference to FIG.6.

The signal 319 is, for example, an output of front-end 104 (FIG. 1). Thesignal 319 is a digital signal with symbol rate S and symbol period 1/S.

The equalizer 320 is operable to process the signal 319 to generatesignal 321. Such processing may comprise, for example, interferencecancellation, level adjustment, filtering, and/or the like. The signal321 is, for example, a digital signal which carries symbols (e.g., QAMsymbols, BPSK symbols, etc.).

The equalization process performed by equalizer 320 may be configured byconfiguration parameters which are updated/replaced at a rate slowerthan 1/D (e.g., they may be static or updated only once per span of manysymbol periods). Since a corrupted configuration parameter couldpotentially result in corruption of every received symbol, theconfiguration parameters may be stored in RDRAM array 304 ₁ to preventthem from being corrupted due to cell leakage. Similarly, theequalization process performed by equalizer 320 may be controlled by aseries of instructions which are updated/replaced at a rate slower than1/D (e.g., they may be static or updated only upon initialization of theSoC 102). Accordingly, since a corrupted instruction could potentiallyresult in corruption of every symbol, the RDRAM array 304 ₁ may be usedas program memory for storing the instructions to prevent theinstructions from being corrupted due to cell leakage. Conversely,values of the incoming data signal 319, values of the outgoing datasignal 321, and temporary values generated/used during equalization, maybe updated/replaced a rate faster than 1/D. Accordingly, such datavalues may be stored in NDRAM array 306 ₁ without increasing theprobability of a critical amount of corruption of such data beyond adesired limit What constitutes a critical amount of corruption isimplementation dependent and based on, for example, a number of symbolerrors than can be corrected or compensated for by downstream componentssuch as decoder 326; a target metric such as a threshold symbol errorrate, a threshold bit error rate, a threshold signal to noise ratio, orthe like (e.g., set forth in a standard with which the SoC 102 is tocomply); and/or end user experience (e.g., in a video scenario, a numberof symbol errors that can be tolerated before the picture is visiblydegraded).

As an example, assuming that up to N (an integer) symbols of signal 319are to be buffered in equalizer 320, then the data values in the buffermay be updated/replaced at a rate of S/N. When S is sufficiently largeand/or N is sufficiently small, then S/N>1/D and the buffering may beperformed in array 306 ₁ without increasing the probability of acritical amount of corruption of such data beyond a desired threshold.Conversely, when S is too small and/or N is too large, then S/N<1/D andthe data may (depending on what is considered a critical amount ofcorruption for the particular implementation) need to be buffered inarray 304 ₁ to prevent a critical amount of corruption due to cellleakage.

The demapper 322 is operable to process the signal 231 to demap each ofthe symbols of signal 321 to one or more binary values, and output thebinary values as signal 323. For example, the demapper 322 may map eachN-QAM symbol of signal 321 to log₂(N) bits of signal 323.

The demapping process performed by demapper 322 may be configured byconfiguration parameters which are replaced/updated at a rate slowerthan 1/D (e.g., they may be static or updated only once per span of manysymbol periods). Accordingly, the configuration parameters may be storedin RDRAM array 304 ₂ to prevent them from being corrupted due to cellleakage. Similarly, the demapping process performed by demapper 322 maybe controlled by a series of instructions which are replaced/updated ata rate slower than 1/D (e.g., they may be static or updated only oninitialization of the SoC 102). Accordingly, the RDRAM array 304 ₂ maybe used as program memory for storing the instructions to prevent theinstructions from being corrupted due to cell leakage. Conversely,values of the incoming data signal 319, values of the outgoing datasignal 323, and temporary values generated/used during demapping, may beupdated/replaced at a rate faster than 1/D. Accordingly, such datavalues may be stored in NDRAM array 306 ₂ without increasing theprobability of a critical amount of corruption of such data beyond adesired limit.

The deinterleaver 324 is operable re-order the bits of signal 323 toundo reordering performed in a transmitter from which the signal 319 wasreceived. The deinterleaving process performed by deinterleaver 324 maybe configured by configuration parameters which are updated/replaced ata rate slower than 1/D (e.g., they may be static or updated only onceper span of many symbol periods). Accordingly, the configurationparameters may be stored in RDRAM array 304 ₃ to prevent them from beingcorrupted due to cell leakage. Similarly, the deinterleaving processperformed by deinterleaver 324 may be controlled by a series ofinstructions which are updated/replaced at a rate slower than 1/D (e.g.,they may be static or updated only on initialization of the SoC 102).Accordingly, the RDRAM array 304 ₃ may be used as program memory forstoring the instructions to prevent the instructions from beingcorrupted due to cell leakage.

In instances that interleaving is performed across boundaries of M (aninteger) symbols, deinterleaving may require buffering M symbols worthof bits of the signal 323 and then completing rearrangement of thosebits before the next M symbols arrive. Accordingly, a value may sit on aDRAM cell of the buffer for up to M symbol periods. Thus, if M/S is lessthan D, the buffering may be performed using NDRAM cells of the array306 ₃ without introducing an unacceptable risk of a critical amount ofdata corruption, and if M/S is greater than D, the buffering may beperformed using RDRAM cells of the array 304 ₃. Interleaving may alsorequire temporarily storing bits that are currently being swapped.Typically, such temporary storage will be for less than D, and thus theNDRAM cells of the array 306 ₃ can be used.

The decoder 326 is operable to decode the signal 325 in accordance withone or more forward error correction (FEC) protocols/algorithms (e.g.,Reed-Solomon, Turbo codes, Low Density Parity Check, and/or the like).The decoding may detect errors in the signal 325 and, in some instances,correct errors in the signal 325 such that signal 327 contains fewererrors.

The decoding process performed by decoder 326 may be configured byconfiguration parameters which are replaced/updated at a rate slowerthan 1/D (e.g., they may be static or updated only once per span of manysymbol periods). Accordingly, the configuration parameters may be storedin RDRAM array 304 ₄ to prevent them from being corrupted due to cellleakage. Similarly, the decoding process performed by decoder 326 may becontrolled by a series of instructions which are replaced/updated at arate slower than 1/D (e.g., they may be static or updated only oninitialization of the SoC 102). Accordingly, the RDRAM array 304 ₄ maybe used as program memory for storing the instructions to prevent theinstructions from being corrupted due to cell leakage.

In instances that an FEC codeword spans K (an integer) symbols,deinterleaving may require buffering K symbols worth of bits of thesignal 325 and then decoding those bits before the next K symbolsarrive. Accordingly, a value may sit on an DRAM cell of the buffer forup to K symbol periods. Thus, if K/S is less than D, the buffering maybe performed using NDRAM cells of the array 306 ₄ without introducing anunacceptable risk of a critical amount of data corruption, and if K/S isgreater than D, the buffering may be performed using RDRAM cells of thearray 304 ₄. Interleaving may also require temporarily storing valuesgenerated during decoding (e.g., messages for a message passing LPDCdecoder). Typically, such temporary storage will be for less than D, andthus the NDRAM cells of the array 306 ₄ can be used.

In an example implementation, SRAM cells, which do not suffer from theleakage problem that DRAM cells do, may be used instead of one or moreof the RDRAM cells of one or more of arrays 304 ₁-304 ₄.

Other circuits which may use one or both of RDRAM and NDRAM include, forexample, a circuit that performs a fast Fourier transform (FFT), acircuit that performs an inverse fast Fourier transform (IFFT), a filter(e.g., finite impulse response (FIR) or infinite impulse response (IIR))memory, an analog-to-digital converter, a digital-to-analog converter,and/or the like.

FIG. 4 depicts an example system which is configurable such that in afirst mode an array of DRAM cells is used as RDRAM and in a second modethe array is used as NDRAM. Shown is another simplified block diagram ofthe SoC 102. The data processing circuit 402 may represent, for example,the processor 112 (FIG. 1), the DSP 106, and/or a portion thereof.

The DRAM array 404 may comprise one or more DRAM cells, such as the “1T”cell shown in FIG. 5A.

The memory refresh circuit 202 may be as described above for example.The rate at which circuit 202 performs refreshes may be controlled bythe control signal 405. When the refresh rate is greater than zero, theDRAM 404 operates as RDRAM. When the refresh rate is zero, the DRAM 404operates as NDRAM.

In such an example implementation, the rate of refreshes of array 404performed by the refresh circuit 202 may be adjusted during run time ofthe SoC 102 based on a performance parameter (e.g., SNR, SER, BER,and/or the like). For example, the rate of refreshes of array 404performed by the refresh circuit 202 may be set to zero (i.e., disabled)when a performance parameter (e.g., SNR, SER, BER, and/or the like) isabove a threshold, and may be set to greater than zero when theperformance parameter is below or equal the threshold.

The rate of refreshes of array 404 performed by the refresh circuit 202may be adjusted based on a communications standard associated withsignals to be transmitted and/or received by the SoC 102. For example,refresh circuitry and/or refreshing of one or more memory cells may bedisabled when the system is transmitting and/or receiving signalsaccording to a first particular standard that requires a first, lowerSNR (and/or other performance metric), and may be enabled when thesystem is receiving and/or transmitting signals of a second particularstandard that requires a second, higher SNR (and/or other performancemetric).

The rate of refreshes of array 404 performed by the refresh circuit 202may be adjusted based on a bit rate and/or symbol rate of data bufferedin the array 404. For example, refreshing of DRAM 404 may be enabledwhen the symbol rate or bit rate is below a threshold and may bedisabled when the bit rate or symbol rate is above the threshold. Therefresh rate may be configured at power-up/initialization and/or mayoccur dynamically as the datastream to which the data belongs is beingreceived or transmitted.

The rate of refreshes of array 404 performed by the refresh circuit 202may be adjusted based on strength of an error correction code in use fordata stored in the array 404. In this regard, a higher code rate maycorrespond to an ability to correct more errors and, thus, more errorsresulting from charge leakage in the array 404 may be tolerated. Forexample, refresh of the array 404 may be enabled when the code rate ofdata being buffered in array 404 is less than a threshold value andrefresh of the array 404 may be disabled when the code rate is greaterthan the threshold value.

FIGS. 6A-6C illustrate aspects of sizing RDRAM and NDRAM cells. Sizingof cells of the RDRAM array 204 and cells of the NDRAM array 206 may bebased on pertinent performance requirements(s) (e.g., tolerable symbolerror rate, tolerable bit error rate, minimum signal to noise ratio,and/or the like), strength of error correction algorithms in use, powerconsumption goals, desired and/or necessary access (read and/or write)times, and/or other parameters that dictate a necessary reliabilityand/or speed of the DRAM cell.

In FIG. 6A, the contents of a first NDRAM cell (i.e., a single cellarray) 206 a are updated/replaced at rate of R1, and the contents of asecond NDRAM cell (i.e. a single-cell array) 206 a are updated/replacedat a rate of R2. Assuming that R2>R1, and that the same probability oferror due to leakage can be tolerated for both cells, then the area of206 a (X1×Y1) may be bigger than the area of 206 b (X2×Y2).

In FIG. 6C, the RDRAM cell is written at a rate of R2 and refreshed at arate of R3 and the NDRAM cell is written at a rate of R2. Even thoughthe NDRAM cell and RDRAM cell are written at the same rate, the RDRAMcell is bigger than the NDRAM cell to accommodate overhead (e.g., power,latency, etc.) caused by the refresh. Thus, assuming that the sameamount of errors due to leakage can be tolerated for both cells, theRDRAM 204 cell is larger than necessary in the case that R2 is fasterthan D. Thus, in an example implementation, when R2 is lower than D, thedata may be routed to cell 204 of FIG. 6C, and when R2 is higher than D,the data may be routed to the cell 206 of FIG. 6C while refresh of cell204 is disabled to conserve energy.

FIGS. 7A-7C depict memory arrays where different types of memory cellsare used for different ones of the cells of a particular memory wordassociated with a particular memory address. Given a RDRAM cell andNDRAM cell of the same size, the RDRAM is less prone to corruption.Accordingly, in some instances, the extra overhead of the RDRAM may bedeemed worthwhile to ensure reliability of certain data while NDRAMcells may be used for data that can tolerate more error. For example,corruption of a more significant bit of a word of data may beunacceptable whereas corruption of a less significant bit of the word ofdata may be more tolerable. Accordingly, RDRAM cells may be used for theMSB(s) and NDRAM cells may be used for the LSB(s), as shown in FIG. 7A.

Even where a word (or words) of data does not have MSB(s) and LSB(s) perse (e.g., the word does not store a single value but a plurality ofseparate fields) corruption of some bits of the word (or words) may havemore of a negative impact on system performance than corruption ofothers. For example, corruption of header bits of a packet may cause theentire packet to be useless whereas corruption of payload bits may havea relatively minor impact. Accordingly, RDRAM cells may be used for themore critical bits and NDRAM cells may be used for the less-criticalbits.

Similarly, rather more-reliable SRAM cells may be mixed with lessreliable RDRAM cells and/or even less-reliable NDRAM cells. An exampleof using SRAM for the MSB(s) of a memory word (or words) and NDRAM ofthe LSB(s) of the memory word (or words) is shown in FIG. 7C.

In accordance with an example implementation of this disclosure, anintegrated circuit (e.g., 102) may comprise a digital logic circuit(e.g., any one or more of 320, 322, 324, and 326), a memory refreshcircuit (e.g., 202), a first one or more dynamic random access memory(DRAM) cells (e.g., 204), and a second one or more eDRAM cells (e.g.,206). The first one or more DRAM cells may be refreshed by the memoryrefresh circuit whereas the second one or more DRAM cells is notrefreshed by any memory refresh circuit. Each of the first one or moreDRAM cells and the second one or more DRAM cells may be a one-transistor(“1T”) cell (e.g., as shown in FIG. 5A).

The first one or more DRAM cells may be used for storage of data whichis overwritten at less than a threshold frequency (e.g., instructionsand/or configuration parameters). The second one or more DRAM cells maybe used for storage of data which is overwritten at greater than thethreshold frequency (e.g., received and/or to-be-transmitted data). Thefirst one or more DRAM cells may be used for storage of a first type ofdata (e.g., packet headers, control channels of an MPEG stream, and/orthe like) for which tolerance of errors is low relative to a second typeof data (e.g., packet payloads, audio data, video data, and/or thelike). The second one or more DRAM cells may be used for storage of thesecond type of data. The first one or more DRAM cells and the second oneor more DRAM cells may be part of a single memory word (i.e., located atthe same address). The first one or more DRAM cells may hold first bitsof data written to the memory word, and the second one or more DRAMcells may hold second bits of data written to the memory word, where thefirst bits of data are more significant than the second bits of data.

A rate at which the memory refresh circuit refreshes the first one ormore DRAM cells may be adjusted during run-time of the integratedcircuit (e.g., as the integrated circuit is receiving and/ortransmitting data via a wired or wireless channel). The adjustment ofthe rate of refresh may comprise an enable of refresh of the first oneor more DRAM cells during a first time interval and a disable of refreshof the first one or more DRAM cells during a second time interval. Theadjustment of the rate of refresh may be based on a forward errorcorrection code rate of data stored in the first one or more DRAM cells(e.g., rate of refresh may decrease as the code rate goes down andincrease as the code rate goes up). The adjustment of the rate ofrefresh may comprise varying the rate of refresh in response tovariations of a symbol rate of signals buffered in the first one or moreDRAM cells.

Other embodiments of the invention may provide a non-transitory computerreadable medium and/or storage medium, and/or a non-transitory machinereadable medium and/or storage medium, having stored thereon, a machinecode and/or a computer program having at least one code sectionexecutable by a machine and/or a computer, thereby causing the machineand/or computer to perform the methods described herein.

Accordingly, the present invention may be realized in hardware,software, or a combination of hardware and software. The presentinvention may be realized in a centralized fashion in at least onecomputing system, or in a distributed fashion where different elementsare spread across several interconnected computing systems. Any kind ofcomputing system or other apparatus adapted for carrying out the methodsdescribed herein is suited. A typical combination of hardware andsoftware may be a general-purpose computing system with a program orother code that, when being loaded and executed, controls the computingsystem such that it carries out the methods described herein. Anothertypical implementation may comprise an application specific integratedcircuit or chip.

The present invention may also be embedded in a computer programproduct, which comprises all the features enabling the implementation ofthe methods described herein, and which when loaded in a computer systemis able to carry out these methods. Computer program in the presentcontext means any expression, in any language, code or notation, of aset of instructions intended to cause a system having an informationprocessing capability to perform a particular function either directlyor after either or both of the following: a) conversion to anotherlanguage, code or notation; b) reproduction in a different materialform.

While the present invention has been described with reference to certainembodiments, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted withoutdeparting from the scope of the present invention. In addition, manymodifications may be made to adapt a particular situation or material tothe teachings of the present invention without departing from its scope.Therefore, it is intended that the present invention not be limited tothe particular embodiment disclosed, but that the present invention willinclude all embodiments falling within the scope of the appended claims.

What is claimed is:
 1. A system comprising: an integrated circuitcomprising a digital logic circuit, a memory refresh circuit, anddynamic random access memory (DRAM) cells, wherein: a first portion ofsaid DRAM cells is refreshed by said memory refresh circuit; said DRAMcells store data received via a communication link; and a rate at whichsaid first portion of said DRAM cells is refreshed is adjusted based ona symbol rate at which said data is received via said communicationlink.
 2. The system of claim 1, wherein said DRAM cells compriseone-transistor (“1T”) cells.
 3. The system of claim 1, wherein saidadjustment of said rate at which said first portion of said DRAM cellsis refreshed comprises an enabling of refresh of said first portion ofsaid DRAM cells by said memory refresh circuit during a first timeinterval and a disabling of refresh of said first portion of said DRAMcells by said memory refresh circuit during a second time interval. 4.The system of claim 1, wherein said adjustment of said rate at whichsaid first portion of said DRAM cells is refreshed is based on a forwarderror correction code rate of said data.
 5. The system of claim 1,wherein: said adjustment of said rate at which said first portion ofsaid DRAM cells is refreshed comprises a disabling of refresh of saidfirst portion of said DRAM cells when said symbol rate is above adetermined threshold; and said adjustment of said rate at which saidfirst portion of said DRAM cells is refreshed comprises an enabling ofrefresh of said first portion of said DRAM cells when said symbol rateis below said determined threshold.
 6. The system of claim 1, whereinsaid adjustment of said rate at which said first portion of said DRAMcells is refreshed is performed during run-time of said integratedcircuit.
 7. A system comprising: an integrated circuit comprising adigital logic circuit, a memory refresh circuit, and dynamic randomaccess memory (DRAM) cells, wherein: a first portion of said DRAM cellsis refreshed by said memory refresh circuit; and a rate at which saidfirst portion of said DRAM cells is refreshed is adjusted based on anon-zero error tolerance of data stored in said first portion of saidDRAM cells.
 8. The system of claim 7, wherein said DRAM cells compriseone-transistor (“1T”) cells.
 9. The system of claim 7, wherein saidadjustment of said rate at which said first portion of said DRAM cellsis refreshed comprises an enabling of refresh of said first portion ofsaid DRAM cells by said memory refresh circuit during a first timeinterval and a disabling of refresh of said first portion of said DRAMcells by said memory refresh circuit during a second time interval. 10.The system of claim 7, wherein said adjustment of said rate at whichsaid first portion of said DRAM cells is refreshed is based on a forwarderror correction code rate of said data.
 11. The system of claim 7,wherein: said adjustment of said rate at which said first portion ofsaid DRAM cells is refreshed comprises a disabling of refresh of saidfirst portion of said DRAM cells when said error tolerance is above adetermined threshold; and said adjustment of said rate at which saidfirst portion of said DRAM cells is refreshed comprises an enabling ofrefresh of said first portion of said DRAM cells when said symbol rateis below said determined threshold
 12. The system of claim 7, whereinsaid adjustment of said rate at which said first portion of said DRAMcells is refreshed is performed during run-time of said integratedcircuit.
 13. A system comprising: an integrated circuit comprising adigital logic circuit, a memory refresh circuit, and dynamic randomaccess memory (DRAM) cells, wherein: a first portion of said DRAM cellsis refreshed by said memory refresh circuit; and a rate at which saidfirst portion of said DRAM cells is refreshed is adjusted based on aforward error correction code rate of data stored in said first portionof said DRAM cells.
 14. The system of claim 13, wherein said DRAM cellscomprise one-transistor (“1T”) cells.
 15. The system of claim 13,wherein said adjustment of said rate at which said first portion of saidDRAM cells is refreshed comprises an enabling of refresh of said firstportion of said DRAM cells by said memory refresh circuit during a firsttime interval and a disabling of refresh of said first portion of saidDRAM cells by said memory refresh circuit during a second time interval.16. The system of claim 13, wherein: said adjustment of said rate atwhich said first portion of said DRAM cells is refreshed comprises adisabling of refresh of said first portion of said DRAM cells when saiderror tolerance is above a determined threshold; and said adjustment ofsaid rate at which said first portion of said DRAM cells is refreshedcomprises an enabling of refresh of said first portion of said DRAMcells when said symbol rate is below said determined threshold
 17. Thesystem of claim 13, wherein said adjustment is performed during run-timeof said integrated circuit.